BC, 2×RT, MT simultaneous operation possible MIL-STD-1553 terminal (parallel interface, SPI interface)
The 3.3V CMOS HI-613x devices provide a complete single or multifunction interface between the host processor and the MIL-STD-1553B bus. It includes BC, MT, and 2×RT, which can be enabled to operate simultaneously in any combination. Users can allocate 64KByte of on-chip SRAM to the device according to application requirements.
■ Host Interface
- HI-6130: 16-Bit Parallel Bus
- HI-6131: 4-Wire Serial Peripheral Interface (SPI)
■ Japanese technical documentation on the MIL-STD-1553 communication standard is available. If you would like to see it, please contact sales@nacelle.co.jp.